岗位要求:
具有blocks和 top-level 的SerDes/data converter版图设计经验;
熟练掌握Virtuoso版图设计工具和Calibre等各类物理验证工具;有先进工艺版图设计经验者优先。
Developing physical layouts for analog building blocks and top-level for SerDes and data converter; performing multi-level design verifications and design quality/integrity checks.
Copyright © 集益威半导体(上海)股份有限公司 版权所有
沪公网安备31011502404231号 备案号:沪ICP备2022024457号